Regviz

Silicon Labs /BGM220PC22HNA /MODEM_S /ANTDIVCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ANTDIVCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/MODEM_S/ANTDIVCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADPRETHRESH0 (DISABLE)ENADPRETHRESH

ENADPRETHRESH=DISABLE

Description

No Description

Fields

ADPRETHRESH

Preamble threshold
ENADPRETHRESH

Enable Preamble threshold

0 (DISABLE): Disable use of Preamble threshold after timing detection

1 (ENABLE): Enable use of Preamble threshold after timing detection

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data